What's your background man? You really seem to know your stuff.
I'm not sure your post is ironic, and that you just disagree with me.
I am only sharing my vision for this type of subject, based on datasheets, test results and my experience in the semiconductor industry.
Many people are mixing pure IPC improvements, with IPC per watt or real in game perf / IPC improvements. And mixed also the IPC per units with the overall IPC.
The comparison between RDNA1 and RDNA2, and also GCN vs RDNA1/2 need to be done at ALU level, removing from the equation the nb of Cores (or align the number), the frequency, the possible new process used and some features such as Infinity cache (which in reality, is not a feature of RDNA2, but a feature of NAVI 21 GPU, as shown by PS5 and XsX die using RDNA2).
To have a big IPC steps, you need one (or mixed) of these factors:
- A bug correction that has affected the previous version (not the case for RDNA)
- A big bottleneck in the architecture solved (as far as I know, not the case for RDNA)
- A new architecture (which was the case for RDNA vs GCN, not for RDNA 1 vs RDNA 2)
RDNA2 is clearly not an architecture change, but a very interesting step which has increased a lot the efficiency of this architecture, mainly the IPC per watt (that's why AMD have clearly communicated for such parameters) and the GPU frequency peak. This gave to AMD the possibility to increase the nb of Cores + higher frequency which has increase the overall IPC of Navi 21 against Navi 10, and to help the constraint due to the small bandwidth increase with Navi 21, they have added the Infinity cache.
This optimization was done in parallel of new functionalities that were added (such as RT), but for me, it's clear that RDNA 2 step has not really increased the IPC compared to RDNA 1 (just few percentage).
And to answer you, I'm working in the semi conductors industry since 2007, started working with memory + memory controller design + place and route work. After that, I mainly switched to analog design and associated physical design + digital integration. I am not an expert on digital circuit design, clearly bigger background for analog design, but I work in a mixed team (Digital experts, analog ones, verification, lab, test etc...).