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AnandTech - Xbox Series X SoC: Power, Thermal, and Yield Tradeoffs

3liteDragon

Member
This week at ISSCC (International Solid State Circuits Conference), Microsoft presented a talk titled ‘Xbox Series X SoC: A Next Generation Gaming Console’, with hardware engineer Paul Paternoster presenting. The 30 minute presentation covered a lot about Microsoft’s latest console processor, most of which was a repeat about what we saw at Hot Chips in August last year, however there was a new element in this presentation talking about how the console design team balanced acoustics, power, thermal performance, and processor yield, discussing where the hotspots in the design originate and where the performance/power targets of the final silicon were optimized.
 
Waiting for the summary. Tks

Edit:

So the CPU is actually the limiting factor regarding power/temperatures. That might be why there are some weird CPU limited scenarios in games on the SX that aren't present on PS5.

For Scarlett, it is actually the CPU that becomes the limiting factor. Using AMD’s high-performance x86 Zen 2 cores, rather than the low power Jaguar cores from the previous generation, combined with how gaming workloads have evolved in the 7 years since, means that when a gaming workload starts to ramp up, the dual 256-bit floating point units on the CPU is where the highest thermal density point happens.

In this slide shown, although it doesn’t indicate what sort of workload is in play here, whether it is an active game or a power virus, Microsoft is showing 87.4ºC at the hotspot on the CPU side, while the GPU only has a 80.9ºC hotspot. Now this also comes down to the frequency choice and design point of the hardware, and finding the right balance between CPU power, GPU power, and overall thermal characteristics and acoustics.
 
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ethomaz

Banned
Waiting for the summary. Tks
AnandTech deserves the read and click :p

Edit - Pics.

ISSCC2021-3_1-page-016_575px.jpg

ISSCC2021-3_1-page-018b2_575px.jpg
 
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M1chl

Currently Gif and Meme Champion
  • A 300 mm wafer has 706.86 cm2 of area
  • A defect rate of 0.09 defects per cm2 means ~64 defects per wafer
  • Scarlett is 306.4 mm2 (15.831 mm x 22.765 mm)
  • Note that SoCs are rectangles, and wafers are circular,
  • Wafer die calculators show that 100% yield of this SoC size would give 147 dies per wafer
  • Microsoft sets the frequency/power such that if all dies are good, all can be used
  • With a 0.09 / cm2 defect rate, there are 107 good dies per wafer
  • This means a 73% yield, 107 / 147
So there we go, it was for yields.
 

ethomaz

Banned
  • A 300 mm wafer has 706.86 cm2 of area
  • A defect rate of 0.09 defects per cm2 means ~64 defects per wafer
  • Scarlett is 306.4 mm2 (15.831 mm x 22.765 mm)
  • Note that SoCs are rectangles, and wafers are circular,
  • Wafer die calculators show that 100% yield of this SoC size would give 147 dies per wafer
  • Microsoft sets the frequency/power such that if all dies are good, all can be used
  • With a 0.09 / cm2 defect rate, there are 107 good dies per wafer
  • This means a 73% yield, 107 / 147
So there we go, it was for yields.
AnandTech estimate that it is a bit better than that with the 26 WGPs config.
They tested two configurations (56 and 52 CUs) and ended with the later to increase yields.

ISSCC2021-3_1-page-034_575px.jpg
 
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RaZoR No1

Member
So in short Heat is one of the limiting factors they currently have?
Even if we should get to dangerously high temps, it still should keep the clocks fixed and therefore we normally shouldnt have these performance drops, but we still have them.

Still nice to see that MS talks more openly about XSX chip design etc.
 

M1chl

Currently Gif and Meme Champion
So in short Heat is one of the limiting factors they currently have?
Even if we should get to dangerously high temps, it still should keep the clocks fixed and therefore we normally shouldnt have these performance drops, but we still have them.

Still nice to see that MS talks more openly about XSX chip design etc.
Well it was limiting factor to build the console, does not seems to have temp issues now. At least I did not get that from reading (still reading) the article. However interesting, that AVX-256 units are the most heated ones, maybe that's why Sony cut them?
 

RaZoR No1

Member
Well it was limiting factor to build the console, does not seems to have temp issues now. At least I did not get that from reading (still reading) the article. However interesting, that AVX-256 units are the most heated ones, maybe that's why Sony cut them?
Are there even any advantages using AVX-256?
All I hear is, it consumes the most power = most heat, lower clocks etc.
If Sony decides to remove that Feature, than it is maybe not that important atm?
 

M1chl

Currently Gif and Meme Champion
Are there even any advantages using AVX-256?
All I hear is, it consumes the most power = most heat, lower clocks etc.
If Sony decides to remove that Feature, than it is maybe not that important atm?
I don't really know honestly.
 

ethomaz

Banned
Are there even any advantages using AVX-256?
All I hear is, it consumes the most power = most heat, lower clocks etc.
If Sony decides to remove that Feature, than it is maybe not that important atm?
I believe Cerny highlighted pretty well it uses vs power of the native 256bits (that includes AVX) support in PS5.
It was the reason why they choose variable frequencies in CPU.

"PlayStation 5 is especially challenging because the CPU supports 256 bit native instructions that consume a lot of power.

These are great here and there but presumably only minimally used or are they if we plan for major 256 bit instruction usage we need to set the CPU clock substantially lower or noticeably increase the size of the power supply and fan."

They choose to lower the CPU clock.
 
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onesvenus

Member
I believe Cerny highlighted pretty well it uses and why they have native AVX256 support in PS5.
It was the reason why they choose variable frequencies in CPU.
Didn't Cerny say that it has "native 256 bit instructions"? Can we assume it was talking about AVX256?
 

M1chl

Currently Gif and Meme Champion
Well based on that chip layout it seems that they are using another part of the chip for that.
 

3liteDragon

Member
Didn't Cerny say that it has "native 256 bit instructions"? Can we assume it was talking about AVX256?
Honestly, I just want a higher-res picture to look at. You got NX Gamer on one hand saying it's 2 128-bit instructions over 2 clock cycles and then you got some people here saying Cerny meant AVX256 when he said "NATIVE 256-bit instructions", so idk.
 

M1chl

Currently Gif and Meme Champion
Honestly, I just want a higher-res picture to look at. You got NX Gamer on one hand saying it's 2 128-bit instructions over 2 clock cycles and then you got some people here saying Cerny meant AVX256 when he said "NATIVE 256-bit instructions", so idk.
If it can do in 2 cycles and can crunch 256-bit instruction is still native, normal 128-bit units cannot get 256bit instruction....
 
Seems more they have simplified and re-layouted (removing redundancy) this part, but kept the AVX256.
 
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onesvenus

Member
AVX-256 is a extension instruction set that uses 256bits SIMD instructions.

BTW I remember in a interview he using the AVX as being the very case of the CPU clocks going lower.
I know what AVX256 is, what I'm asking is if he was talking about that or you are just assuming. Zen CPUs have other 256 instructions
 
If it can do in 2 cycles and can crunch 256-bit instruction is still native, normal 128-bit units cannot get 256bit instruction....

As he was speaking about the huge power used by this part when discussing about the 256bits instructions, for me that could give us the clue that they kept the AVX256.
 

ethomaz

Banned
I know what AVX256 is, what I'm asking is if he was talking about that or you are just assuming. Zen CPUs have other 256 instructions
I don't remember... it was a Digital Foundry interview... he maybe said heavy 256bits instructions and Richard could had said like AVX.
He just hinted that when used these instructions the CPU clock can go lower but in most case it stay basically at 100%.

The interview after all was not Cerny talking but Richard telling what Cerny said to him.
 
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Rikkori

Member
That's some really cool details there for all the hardware dorks like me. Very interesting about the yields, it's definitely a major factor in deciding to release any product - after all, more dies = more consoles = more users to spend money. It's not like they're in it to make money from hardware sales themselves.
 

Fredrik

Member
I guess I got my answer there why they run the GPU so slowly. Heat because of that AVX256 thingy. Only time will tell if that was clever. Bummer that they can’t retrofit a higher clock though.
 

ethomaz

Banned
I guess I got my answer there why they run the GPU so slowly. Heat because of that AVX256 thingy. Only time will tell if that was clever. Bummer that they can’t retrofit a higher clock though.
ABX256 affect CPU hear only... not GPU.
If you look at the heat diagram between the CPU and GPU there is a cool part of the SoC.
 
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Lysandros

Member
Honestly, I just want a higher-res picture to look at. You got NX Gamer on one hand saying it's 2 128-bit instructions over 2 clock cycles and then you got some people here saying Cerny meant AVX256 when he said "NATIVE 256-bit instructions", so idk.
NXgamer is just speculating on Locuza's first guess (he changed his mind after further contribution btw.), 2x128-bit can't be considered native AVX-256 as far i know it has to be 1x256-bit (at the very same 256-bit FPU width, hence the term native). Cerny very clearly said native 256-bit instructions in Road to PS5.
 

ethomaz

Banned
Okay so they could, theoretically, boost the GPU clock without hitting the heat ceiling?
They can but seems like they choose the actual frequencies due the yield.

“Microsoft sets the frequency/power such that if all dies are good, all can be used”

That all chips produced can reach that minimum frequency/power... they could not guarantee that minimum if they go higher with the clocks.
 
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Fredrik

Member
They can but seems like they choose the actual frequencies due the yield.

“Microsoft sets the frequency/power such that if all dies are good, all can be used”

That all chips produced can reach that minimum frequency/power... they could not guarantee that minimum if they clinchers the clocks.
Thanks, it’s not right to say it’s an oversight but this will probably haunt them all gen, there are always certain games and scenarios where a higher clock is better.
 
Waiting for the summary. Tks

Edit:

So the CPU is actually the limiting factor regarding power/temperatures. That might be why there are some weird CPU limited scenarios in games on the SX that aren't present on PS5.

Hm....boottleneck intensifies

NX seems to have a new full analysis from AC that shows the CPU is the big issue on Series X performance.

If that turns true then I believe in points:

1) Xbox OS is taking too much CPU
2) Xbox has less dedicated units to offload a lot of tasks from the CPU like PS5 has






  • A 300 mm wafer has 706.86 cm2 of area
  • A defect rate of 0.09 defects per cm2 means ~64 defects per wafer
  • Scarlett is 306.4 mm2 (15.831 mm x 22.765 mm)
  • Note that SoCs are rectangles, and wafers are circular,
  • Wafer die calculators show that 100% yield of this SoC size would give 147 dies per wafer
  • Microsoft sets the frequency/power such that if all dies are good, all can be used
  • With a 0.09 / cm2 defect rate, there are 107 good dies per wafer
  • This means a 73% yield, 107 / 147
So there we go, it was for yields.


They can but seems like they choose the actual frequencies due the yield.

“Microsoft sets the frequency/power such that if all dies are good, all can be used”

That all chips produced can reach that minimum frequency/power... they could not guarantee that minimum if they go higher with the clocks.

Thanks, it’s not right to say it’s an oversight but this will probably haunt them all gen, there are always certain games and scenarios where a higher clock is better.

Maybe also because of yields they've to chose 25% perf/clock on XSX??
 
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Hm....boottleneck intensifies















Maybe also because of yields they've to chose 25% perf/clock on XSX??


They choose 25% perf/clock? That's a nonsense in fact. The IPC is linked to the architecture used compared to other one.The yield is linked to the specs choosed for the die, in this case it seems they choose to reduce the frequency to limit the power consumption. But the IPC was not changed.

For the tweet from LeviathanGamer, I'm really surprised that this layout could generate a bottleneck. When the place/route step is done, all is done to keep the timing as needed using the right buffers and keep the signal integrity, etc... Same work done to verify the hot spots in the die, to verify the pollution from an area to another.
 
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They choose 25% perf/clock? That's a nonsense in fact. The IPC is linked to the architecture used compared to other one.The yield is linked to the specs choosed for the die, in this case it seems they choose to reduce the frequency to limit the power consumption. But the IPC was not changed.

For the tweet from LeviathanGamer, I'm really surprised that this layout could generate a bottleneck. When the place/route step is done, all is done to keep the timing as needed using the right buffers and keep the signal integrity, etc... Same work done to verify the hot spots in the die, to verify the pollution from an area to another.

In fact, it is not! Clock would be higher if they chose over 25%, right. And power consumption lower??

But anyway, same from Anandtech

MS confirmed 25% in their HotChips presentation.
They boasted 25% performance increase in CU perf/clock from Xbox One X (GCN) to Series X.


I’m not even sure where you are getting 50% lol

and

Here is the official full HotChips conference for XSX.


Architecturally these CUs have 25% better performance per clock on average graphics workloads relative to the GCN generation

UpNlOnE.jpg


Timestamped at 16:50

 
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In fact, it is not! Clock would be higher if they chose over 25%, right. And power consumption lower??
But anyway, same from Anandtech



and

Here is the official full HotChips conference for XSX.




UpNlOnE.jpg


Timestamped at 16:50



In fact, the IPC increase shared by MS is simply in reality the increase between RDNA1&2 and GCN. That's all.
 
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martino

Member
In fact, the IPC increase shared by MS is simply in reality the increase between RDNA1&2 and GCN. That's all.
no. but
AMD will disclose more about RDNA2 and its optimizations later on in their full tech deep dives, but for today there are offering a high-level overview focusing on the three big sources of efficiency gains for RDNA2: more energy-efficient CUs, higher frequencies at the same power levels, and an increase in real-world perf-per-clock/IPC thanks to the Infinity Cache.
we know why.
 
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In reality, RDNA 1 and 2 architectures offered similar IPC. And your message is clearly explaining that, with 6x00 cards, the increased in performances is due to higher frequencies and real-world perf per clock/IPC thanks to Infinity cache usage. Not the IPC, which is between these two RDNA steps pretty similar.
Between RDNA and GCN, yes the IPC is increased by 25%.
 
In fact, the IPC increase shared by MS is simply in reality the increase between RDNA1&2 and GCN. That's all.

Percentage increase from GCN to RDNA 2 would be much higher and surely they would mentioned that number. They literally said from GCN to RDNA1. Which is 25%. As they've said during presentation.
 
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Percentage increase from GCN to RDNA 2 would be much higher and surely they would mentioned that number. They literally said from GCN to RDNA1. Which is 25%. As they've said during presentation.

In fact, RDNA 2 has increased the IPC per watt, but the IPC is pretty similar with RDNA (just few percentages of increase). RDNA 2 is an upgraded version, with new functionnalities such as RT, MS (etc...) plus optimisation to increase efficiency: reduce the consumption + higher frequency.
 
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longdi

Banned
Waiting for the summary. Tks

Edit:

So the CPU is actually the limiting factor regarding power/temperatures. That might be why there are some weird CPU limited scenarios in games on the SX that aren't present on PS5.

no....all zen2 chiplets run hot when pushed because they are small and have high thermal density. but ms has guaranteed a sustained performance across their soc and ssd, so it won't throttle and become a limiting factor compared to ps5
 
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no....all zen2 chiplets run hot when pushed because they are small and have high thermal density. but ms has guaranteed a sustained performance across their soc and ssd, so it won't throttle and become a limiting factor compared to ps5
The XsX has shutdowns and crashes with certain games still, so either they haven’t solved all the thermals or the responsibility gets put on the devs not to overload the cpu.
 

quest

Not Banned from OT
probably games related bugs rather than thermal issues?
We saw bugs like that in the last few years affect both Xboxes and playstations. Call of duty did it last for example.

 

01011001

Banned
Waiting for the summary. Tks

Edit:

So the CPU is actually the limiting factor regarding power/temperatures. That might be why there are some weird CPU limited scenarios in games on the SX that aren't present on PS5.

what? you are aware that both use basically identical cores, and the Xbox ones are clocked higher at literally all time right? the "limiting factor" described is based on the form factor, the cooling solution and how high they could clock them.
 
This goes well with my theory that PS5 seems to be punching above its weight on old games because it can downclock the CPU (since old games are based on Jaguar and Zen 2 can run them in its sleep) while the XSX can't and thermals start cockblocking it. Will be interesting to see what happens once we get actual next-gen games that need all the CPU power.
 

DaGwaphics

Member
what? you are aware that both use basically identical cores, and the Xbox ones are clocked higher at literally all time right? the "limiting factor" described is based on the form factor, the cooling solution and how high they could clock them.

This is some bizarre new narrative. Like you said, If the chips had run cooler they would have run them at 4ghz or 4.2ghz, etc.
 
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