LordOfChaos
Member
AMD INFINITY CACHE Trademark Application of Advanced Micro Devices, Inc. - Serial Number 90222772 :: Justia Trademarks
Integrated circuits, namely, graphics, video and multimedia integrated circuits; integrated circuit chip sets; cards containing integrated circuits; integrated circuit chips; semiconductor devices; semiconductor chips; semiconductors; chipsets; computer hardware; microprocessors; microprocessor...
trademarks.justia.com
Alright, basic gist, makes the new shared L1 in RDNA more effective (higher hit rates) by dynamically clustering CUs together, to pool their cache lines, to minimize duplication of cache use (+effective capacity) and increase hit rate. This reduces pressure on LLC/L2.
This makes the L2 more effective, thereby reducing pressure on memory bandwidth. This kind of design is enabled by the change in RDNA 1, with a 128KB shared L1 for the CUs within a shader array.
I still think the 128KB is too small for so many CUs, so one of the key changes I expect to see in RDNA 2 is at least 2x L1 size. Combine with this dynamic L1 changes, would be much more potent cache system, both L1 & L2 effective capacity & hit rate up.
Even more tl;dr, moar cache = moar better, dynamic sharing possibly even betterer