Hmm, I didn't know Sony liked staying up-to-date with the WiFi standards if they're around by the time they drop a new system. Not unfeasible they would have WiFi 7 support if it's around by then.Yeah maybe LPDDR4 would make more sense. They do have 512 MB of that for the SSD already. But if the SSD gets doubled to 1.65 TB in size, Sony might want to double that cache as well to 1 GB of LPDDR4. So maybe they'd need to add 1 GB extra for OS, so 2 GB total.
Its just to free up more of the G6 for devs. They did that with PS4 Pro. They went from 256 MB DDR3 on launch PS4 to 1 GB DDR3 on PS4 Pro that was used for the OS and they gave devs more of the G5 for games.
As for the Wifi, I just assume it will progress over time. Sony uses the latest spec most of the time.
PS4 - WiFi 4 (802.11n), Bluetooth 2.1
PS4 Pro - WiFi 5 (802.11ac), Bluetooth 4.0
PS5 - WiFi 6 (802.11ax), Bluetooth 5.1
PS5 Pro - WiFi 7 (802.11be), Bluetooth 6
PS6 - WiFi 8 (802.11?), Bluetooth 7
Just seems likely. Unless the WiFi standards aren't ready in time.
Though like you said, it's up in the air if it'll actually be around by the time of a mid-gen refresh. And as far as further improvements regarding that are concerned, hopefully a doubling of the current top-end channel bandwidth (160 MHz < 320 MHz) and more MU-MIMO streams/antenna support come along, even if it's not double WiFi 6's current limit of 8.
TBH I'm not sure how I derived the 11.3 TF either; I know in hindsight I probably messed something up, but at the time I wrote the OP I believe I took the PS5 chip design as it stands and added in the perf gains by going to N5P, but didn't know how to express that outside of just writing 11.3 TF. It might've been better to just say it as 10.275 TF on such a node equivalent to 11.3 TF on the older N7P process, if the design stayed the same. But any design changes to chip architecture would just "absorb" that performance gain and then some, but then that wouldn't need the funky calculation I did in the OP.Not sure where you're getting 11.3TF @2.23GHz from - thats not how FLOPs are calculated. Its fairly simple mathematics.
36CU = 2304 shaders (64 shaders per Compute unit) = 4608 fused multiply-add floating point operations per clock (2 operations per shader).
Multiply 4608 by 2.23GHz, and you get 10,275 GFLOPS of compute or 10.28 TFLOPS
In order to get 11.3TF, you would 2535 shaders which is not divisible by 64 and therefore not a viable configuration. The only alternative would be 2560 shaders (40CU), which at 2.23GHz would net you 11.4 TFLOPS.
TeraFLOPS is simply a metric to measure how many floating point operations can be performed by a GPU per second.
Also, I doubt Sony would make a PS5 Pro thats barely 10% faster than the base PS5. If they're going to be using chiplets, they could easily configure a set with 3x 20CU chiplets for a total of 60CU. 2 CU disabled per chiplet for a total of 54 CU active.
This nets you 3456 active shaders. 5nm should allow for higher clockspeeds than 7nm, but lets not go too crazy for a power-limited console - say 2.3GHz.
This would net you 15.9 TFLOPS, which is perfectly acceptable for a mid-generation refresh. The great thing about this approach is that 1 chiplet can be kept active for PS4 back compat, 2 chiplets for PS4 Pro and PS5 base back compat, and all 3 chiplets for PS5 Pro boost mode.
Will they go for a chiplet approach for a hypothetical PS5 Pro? I don't know. The benefit of chiplets is that the dies will be smaller and thus more manufacturable, which means the yields will be much higher as you can churn out considerably more of them on a given wafer. On 5nm, 20CU chiplets would be positively tiny. The biggest die will undoubtedly be the I/O complex die. Which they can of course make a nice big one for the PS5 Pro, and then cut it down based on bins for a PS5 Slim refresh with just 2 chiplets as needed. HBMX for PS5 Pro is a resounding no. Probably will keep 16GB of RAM, or will at most add a secondary separate pool of DDR5 RAM along with a co-processor for the OS to free up more of the VRAM for gaming.
I also agree that a PS5 Pro that's only 10% faster than base PS5 can't really be called a "Pro" model but, I don't know if they would actually want to go wider as you say, either. Because Sony's BC is hardware-based, if they went with a 54 CU PS5 Pro, that forces them to a minimum 54 CU PS6, or drop PS5 Pro BC if they wish to keep to a smaller chip for PS6. Smaller nodes are only getting more expensive, not less, and Cerny seems to prefer smaller chips that can get more work done by going faster.
We also can't underestimate the role of hardware accelerated engines becoming more and more important in embedded design systems going forward. We can see that already when you look at stuff like the M1 chip from Apple, and other examples too. Dedicated silicon with a specialized purpose that can save on space and power consumption costs, and ultimately save on costs, that's going to be very big in terms of future focus for a lot of embedded systems and even GPU designs going forward.
Sticking to the hardware-based BC that Cerny and the PS team seem to prefer, if they went 54 CUs for a PS5 Pro and wanted to retain BC for PS6 and give it a notable boost, they'd either be stuck with 54 CU as their floor, and a minimum raise to 72 CUs. Then that starts to ask if that sticks to their "narrow and fast" design philosophy; although that's relative compared to what would be considered as "Big Navi" in 3-4 years' time, again it asks the question of what a good balance would be when you already also have specialized features getting baked into the silicon for hardware acceleration of specific tasks looking like the better alternative to sheer scale of more generic compute capability.
I dunno if chiplets can help with the increasing costs of monolithic dies on smaller nodes, but I'm guessing they'd help at least a bit. In any case any hypothetical PS5 Pro is up in the air regards it being a chiplet or not (same can be said of any hypothetical Series X or S midgen refreshes), but PS6 will absolutely be a chiplet design, probably with some form of PoP vertical 3D die stacking to try keeping the footprint smaller for size.