Is it really that severe? If it really is that bad they should have just ate the cost of the cache. Or gone with less cores and more cache.
There's a reason a CPU is mostly cache: every cache miss means going out to RAM, during which the core is twiddling its thumbs for hundreds of CPU cycles. If you look at a modern CPU, as little as 10% of it will be devoted ALUs and FPUs. An overwhelming percentage of the transistor budget is devoted to the various caches: L1, L2, L3, instruction.
Zen2 die:
source:
https://en.wikichip.org/wiki/File:amd_zen_ccx_2_(annotated).png
Zen2 core:
source:
https://forums.anandtech.com/threads/annotated-hi-res-core-die-shots-of-zen-1-and-2.2577382/
PS5 SOC, with the Zen2 cores on the left:
source:
https://videocardz.com/newz/sony-playstation-5-soc-die-pictured-up-close
An 8-core Zen2 die is called a CCD and is divided into two groups of 4 cores. Each group of 4 cores is called a CCX. On desktop, each CCX has 16MB of L3 cache. Console variants have 8MB per CCX. On Zen2, if a CCX wants to access the L3 cache on the other CCX, it still has to go out to the central IO die, which is very inefficient (
Anandtech). Hence why Zen3 merged the L3 caches. Indeed, a future iteration of Zen3 is reported to triple the size of the L3 cache: an additional 64MB of cache per core cluster (
Reddit).
PS5 I believe is based on the 4700G. The Zen2 desktop was the 3000 series, Zen2 mobile was the 4000 series. In contrast, the 5000 series simplifies the naming by encompassing both Zen3 desktop and mobile CPUs.
As to why both consoles don't have the large L3 caches of desktop CPU: it eats up huge amounts of die space. They're competing for transistors with the GPU so console designers have to balance the demands of both.
